This invention relates to differential amplifiers and to clock duty cycle integrators.
Differential amplifiers are used for a variety of purposes. One use of a differential amplifier is in a circuit that measures and corrects for duty cycle error in a clock signal.
A clock is typically desired to have a 50% duty cycle. A duty cycle integrator is used to produce a differential output voltage that represents the integral of the duty cycle error on a clock signal over time. That voltage is then used to correct the duty cycle of the signal back to 50%.
FIG. 1 shows a simplified prior art duty cycle integrator 10. As input, the duty cycle integrator accepts complementary clock inputs CLK+ and CLKxe2x88x92, and produces a differential output voltage on nodes OUT+ and OUTxe2x88x92.
Duty cycle integrator 10 comprises a differential pair of transistors M1 and M2. The transistors in this example are n-channel MOSFETs whose sources are connected in common to a lower supply voltage Vss. The drain of each transistor is connected to an upper supply voltage Vdd through a load circuit 12. The load circuit typically provides a bias and preferably exhibits high differential mode impedance to facilitate integration of the duty cycle error.
A capacitance C is connected to integrate the output current and generate voltages OUT+ and OUTxe2x88x92.
The gates of transistor M1 and M2 receive the complementary clock inputs CLK+ and CLKxe2x88x92, and the transistors switch on and off in response. Because of the complementary nature of the clock inputs, one transistor is on while the other is off. If there is a 50% duty cycle, each transistor is on for same duration, and the integrated outputs equal each other. If there is other than a 50% duty cycle, however, one of the transistors is on for longer durations than the other transistor. Over time, this causes the integrated outputs OUT+ and OUTxe2x88x92 to become unequal, producing a differential signal. The rate of change of that differential signal is indicative of the duty cycle error on the clock inputs.
FIG. 2 shows a prior art duty cycle integrator 20 having an active load. Transistors M1 and M2 are connected as in FIG. 1, except that a current source I is connected between Vss and the common sources of the transistors. The load comprises two pairs 21 and 22 of p-channel MOSFETs. Each pair has its drains connected in common to the drain of a corresponding one of transistors M1 and M2, and its sources connected in common to Vdd. Within each pair, the gate of one transistor is tied to the drain of the corresponding one of differential transistors M1 and M2, while the gate of the other transistor is tied to the drain of the other, opposing one of differential transistors M1 and M2. For example, of the pair 21, one transistor has its gate tied to the drain of differential transistor M1, while the other transistor has its gate tied to the drain of differential transistor M2.
This load is advantageous in certain situations because it exhibits a very low common mode impedance and a very high differential impedance.
A load such as this is described in U.S. Pat. No. 5,422,529, entitled xe2x80x9cDifferential Charge Pump Circuit With High Differential and Low Common Mode Impedance,xe2x80x9d which states that the described load eliminates the need for common mode feedback.